Many audio applications, such as audio analog to digital converters (ADCs) and audio encoder—decoders (CODECs), utilize a serial data port to transmit digitized audio data to other devices in a system. A typical audio serial data output port outputs bits of a serial audio data (SDOUT) stream in response to an associated serial clock (SCLK) signal. In a stereo system, two channels of audio data are time-multiplexed onto the SDOUT stream with a left-right clock (LRCK) signal. Overall timing is controlled by a master clock (MCLK) signal. At the integrated circuit level, the utilization of a serial port advantageously minimizes the number of pins and associated on-chip driver circuitry.
A typical serial data port operates in either a master mode or a slave mode. In the master mode, the SCLK and LRCK clock signals are generated internally, in response to a received MCLK signal, and output to the destination of the SDOUT stream. In the slave (asynchronous) mode, the SCLK and LRCK clock signals are received from the destination of the SDOUT stream, and therefore may have arbitrary phase relationships with the SDOUT stream.
In an ADC, the analog input signal is typically sampled on corresponding rising edges of an internal MCLK clock signal, while data are output on the falling edges of the SCLK signal. One frequent problem experienced with ADC serial output ports is the coupling of digital noise into the device substrate from the serial output driver at the SDOUT output, especially when the SDOUT output is driving a relatively high load. For example, if a bit of the SDOUT stream is output on a falling edge of the SCLK clock signal occurring slightly before the next sample of the analog input is sampled on the next rising edge of the MCLK signal, digital noise will couple into the ADC analog circuitry through the chip substrate and/or metal lines.
In the past, the problem of substrate noise generated by the SDOUT output driver has been addressed by re-timing the SCLK clock signal relative to the MCLK clock signal, such that the SDOUT output switching and analog input sampling operations are separated sufficiently in time to prevent digital noise in the substrate from being captured by the analog circuitry. However, in the slave mode, in which the SCLK signal is typically received with an arbitrary phase relationship with the external and/or internal MCLK signals, re-timing is difficult.
The problem of noise management is compounded when the LRCK signal is taken into account. At the edges of the LRCK signal, the serial port switches between data channels, which can generate substrate noise dependent on the LRCK signal as the output driver switches, depending on the state of the two channels at the switching event. At the same time, the first bit of the next channel must be available for a sufficient time period between the controlling edge of the LRCK signal and the next falling edge of the SCLK clock signal, which clocks out the second bit, such that the receiving device or system has sufficient time to capture that first bit.
Given the prevalence of serial ports in many data processing applications, and the general need to minimize noise within individual devices and systems, new noise management techniques suitable for serial port applications are desirable. In particular, these techniques should minimize noise occurring at transitions of a frame clock, such as the LRCK signal commonly used in audio applications. In addition to minimizing noise, such techniques should ensure that the first bit transmitted after switching frames is valid for a sufficient time for a receiving device or system to capture.